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Preliminary
RT8012A
Dual 1A/1.5A-1.2MHz Synchronous Step-Down Converters
General Description
The RT8012A is a dual PWM, current mode, stepdown converter. Its input voltage range is from 2.6V to 5.5V and has a constant 1.2MHz switching frequency, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. Each output voltage is adjustable from 0.8V to 5V. Internal power switches with low on-resistance of the dual step-down regulators increase efficiency and eliminate the need for external Schottky diodes. The RT8012A can run at 100% duty cycle for low dropout operation that extends battery life in portable systems. With independent Enable and Power-Good pins, it is easy to control the power up sequence of the two converters, which is important in some applications.
Features
High Efficiency : Up to 95% 1.2MHZ Constant Switching Frequency 1A and 1.5A Load Current on Each Channel Respectively Low RDS(ON) Internal Switches No Schottky Diode Required 0.8V Reference Allows Low Output Voltage Low Dropout Operation : 100% Duty Cycle Internally Compensated < 2A Shutdown Current Power Good Output Voltage Monitor Internal Soft-Start Easy Power Sequence Control Over temperature Protection Short Circuit Protection Thermally Enhanced 16-Lead WQFN Package RoHS Compliant and 100% Lead (Pb)-Free
Ordering Information
RT8012A Package Type QW : WQFN-16L 4x4 (W-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Applications
Portable Instruments Microprocessors and DSP Core Supplies Cellular Phones Wireless and DSL Modems PC Cards Digital Cameras
Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating.
Pin Configurations
(TOP VIEW)
GND PGOOD1
12
For marking information, contact our sales representative directly or through a RichTek distributor located in your area, otherwise visit our website for detail.
FB2 EN2
Marking Information
PGOOD2 PVDD2 PVDD2 PGND
1 2 3 4
16 15 14 13
FB1
PGND
11 10
EN1 VDD 9 PVDD1
5
6
7
8
WQFN-16L 4x4
DS8012A-01 March 2007
LX1 PGND
LX2
LX2
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RT8012A
Typical Application Circuit
VIN 5V R1 100k PGOOD2 Chip Enable VOUT2 1.2V/1.5A C1 10uF
Preliminary
2, 3 10 PVDD2 VDD
9 PVDD1
C2 10uF PGOOD1 13
R2 100k PGOOD1 Chip Enable
1 PGOOD2 15 L1 2.2uH 5, 6 R3 100k 15 EN2 LX2
RT8012A
EN1 11 LX1 7 12 L2 3.3uH R6 625k
VOUT1 3.3V/1.0A
GND
FB2
PGND
FB1
C3 22uF
R4 200k
14
4
R5 200k
C4 10uF
Figure 1. Dual Output 3.3V and 1.2V Step Down Regulators
VIN 5V R1 100k PGOOD2 C1 10uF
2, 3 10 PVDD2 VDD
9 PVDD1
C2 10uF PGOOD1 13 Chip Enable L2 3.3uH R5 625k
1 PGOOD2 15 EN2 LX2
VOUT2 1.2V/1.5A C5 0.1uF
L1 2.2uH 5, 6 R2 100k 15
RT8012A
EN1 11 LX1 7 12
VOUT1 3.3V/1.0A
GND
FB2
PGND
FB1
C3 22uF
R3 200k
14
4
R4 200k
C4 10uF
Figure 2. Dual Output 3.3V and 1.2V Step Down Regulators (Power up sequence is 3.3V first and then 1.2V).
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DS8012A-01 March 2007
Preliminary Functional Pin Description
Pin Number 1 2,3 4,8, Exposed Pad 5,6 7 9 10 Pin Name PGOOD2 PVDD2 PGND LX2 LX1 PVDD1 VDD Pin Function
RT8012A
Power Good Indicator of Regulator 2. Open-drain logic output that is opened when the output voltage exceeds 90% of the regulation point. Power Input Supply of Regulator 2. Decouple this pin to PGND with a capacitor. Power Ground. Exposed pad should be soldered to PCB board and connected to GND. Internal Power MOSFET Switches Output of Regulator 2. Connect this pin to the inductor. Internal Power MOSFET Switches Output of Regulator 1. Connect this pin to the inductor. Power Input Supply of Regulator 1. Decouple this pin to PGND with a capacitor. Signal Input Supply. Decouple this pin to GND with a capacitor. Normally VDD is equal to PVDD1 and PVDD2. Keep the voltage difference between VDD, PVDD1 and PVDD2 less than 0.5V. Regulator 1 Chip Enable. A logic high level at this pin enables Regulator 1, while a logic low level causes Regulator 1 to shut down. Feedback Pin of Regulator 1. Receives the feedback voltage from a resistive divider connected across the output. Power Good Indicator of Regulator 1. Open-drain logic output that is opened when the output voltage exceeds 90% of the regulation point. Signal Ground. Return the feedback resistive dividers to this ground, which in turn connects to PGND at one point. Regulator 2 Chip Enable. A logical high level at this pin enables regulator 2, while a logic low level causes Regulator 2 to shut down. A 1A pull up current from VDD will be injected to EN2 pin when Regulator 1 is ready (VFB1 exceeds 90% of regulation point). Tie this pin to PGOOD1 and add a capacitor between this pin and GND will introduce a delay time before enabling Regulator 2. The delay time can be adjusted by different capacitance. Feedback Pin of Regulator 2. Receives the feedback voltage from a resistive divider connected across the output.
11 12 13 14
EN1 FB1 PGOOD1 GND
15
EN2
16
FB2
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RT8012A
Function Block Diagram
Regulator 1, 2
Preliminary
ISEN Slope Compensation
PVDD1/ PVDD2
OSC 0.8V EA Output Clamp InternalSoft Start 0.72V 0.4V OTP VDD GND EN1/ EN2 EN & SHDN EN1 EN2 Shutdown POR VREF PGOOD1/ PGOOD2 Control Logic OC Limit
FB1/ FB2
Driver
LX1/ LX2
PGND
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Preliminary Absolute Maximum Ratings
(Note 1)
RT8012A
Supply Input Voltage, VDD, PVDD1, PVDD2 --------------------------------------------------------------- -0.3V to 6V LX1, LX2 Pin Voltage --------------------------------------------------------------------------------------------- -0.3V to (VDD + 0.3V) Other I/O Pin Voltages ------------------------------------------------------------------------------------------- -0.3V to 6V Power Dissipation, PD @ TA = 25C WQFN-16L 4x4 ---------------------------------------------------------------------------------------------------- 1.852W Package Thermal Resistance (Note 4) WQFN-16L 4x4, JA ----------------------------------------------------------------------------------------------- 54C/W WQFN-16L 4x4, JC ---------------------------------------------------------------------------------------------- 7C/W Junction Temperature --------------------------------------------------------------------------------------------- 150C Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260C Storage Temperature Range ------------------------------------------------------------------------------------ -65C to 150C ESD Susceptibility (Note 2) HBM (Human Body Mode) -------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ---------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
Supply Input Voltage, VDD, PVDD1, PVDD2 --------------------------------------------------------------- 2.6V to 5.5V Junction Temperature Range ------------------------------------------------------------------------------------ -40C to 125C Ambient Temperature Range ------------------------------------------------------------------------------------ -40C to 85C
Electrical Characteristics
Parameter Input Voltage Range Feedback Reference Voltage DC Bias Current (PVDD1, PVDD2, VDD total)
(PVDD1 = PVDD2 = VDD = 3.6V, TA = 25C, unless otherwise specified)
Symbol VDD VREF
Test Conditions
Min 2.6 0.784
Typ -0.8 830 -2.43 150 0.72 -1.2 --1 200 100 1
Max 5.5 0.816 1100 2 2.55 -0.76 100 1.4 -0.4 1.15 -130 --
Units V V A A V mV V MHz V V V mV ms A
Active, not Switching, VFB1, VFB1 = 0.75V EN1, EN2 = 0 VDD Rising VDD Hysteresis
500 -2.3 -0.68 --
Under Voltage Lockout Threshold FB Threshold for PGOOD Transition PGOOD Pull-Down Resistance Switching Frequency EN1 Input High EN1 Input Low EN2 Threshold EN2 Delay EN2 Pull-up current (Note 5)
Switching Frequency
1.0 1.4 --
EN2 Rising EN2 Hysteresis C5 = 0.1uF
0.85 -70 --
To be continued
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RT8012A
Parameter Regulator 1 Switch On Resistance, High Switch On Resistance, Low Peak Current Limit Output Voltage Line Regulation Output Voltage Load Regulation Regulator 2 Switch On Resistance, High Switch On Resistance, Low Peak Current Limit Output Voltage Line Regulation Output Voltage Load Regulation Symbol
Preliminary
Test Conditions Min Typ Max Units
RFET_H ISW = 0.2A RFET_L ISW = 0.2A ILIM VIN = 2.6V to 5.5V Measured by sever loop, EA output from 0.773V to 1.376V
--1.2 ---
300 260 1.6 ---
450 390 2.2 1 1
m m A %V %
RFET_H ISW = 0.5A RFET_L ISW = 0.5A ILIM VIN = 2.6V to 5.5V Measured by sever loop, EA output from 0.336V to 0.948V
--1.7 ---
180 90 2.2 ---
300 150 3 1 1
m m A %V %
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. JA is measured in the natural convection at TA = 25C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of JC is on the expose pad for the QFN package. Note 5. EN2 pull-up current only is activated when Regulator-1 is ready (VFB1 > 0.72V). No pull-up current (<0.1A) appear when VFB1 < 0.72V.
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Preliminary Typical Operating Characteristics
Regulator 1 Efficiency vs. Output Current
100 90 80
100 90 80
RT8012A
Regulator 2 Efficiency vs. Output Current
Efficiency (%)
60 50 40 30 20 10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Efficiency (%)
VIN = 5V, VOUT = 3.3V L = 3.3uH, COUT = 10uF
70
70 60 50 40 30 20 10 0 0.00 0.25 0.50 0.75
VIN = 5V, VOUT = 1.2V L = 2.2uH, COUT = 10uF
1.00 1.25 1.50
Output Current (A)
Output Current (A)
Regulator 1 Load Transient Response
VIN = 5V, VOUT = 3.3V, IOUT = 0A to 1A L = 3.3uH, COUT = 10uF
Regulator 2 Load Transient Response
VIN = 5V, VOUT = 1.2V, IOUT = 0A to 1.5A L = 2.2uH, COUT = 10uF
VOUT (50mV/Div)
VOUT (50mV/Div)
IOUT (500mA/Div) Time (100s/Div)
IOUT (500mA/Div) Time (100s/Div)
Regulator 1 Load Transient Response
Regulator 2 Load Transient Response
VOUT (50mV/Div)
VOUT (50mV/Div)
IOUT (500mA/Div)
VIN = 5V, VOUT = 3.3V, IOUT = 200mA to 600mA L = 3.3uH, COUT = 10uF
IOUT (500mA/Div)
VIN = 5V, VOUT = 1.2V, IOUT = 200mA to 800mA L = 2.2uH, COUT = 10uF
Time (100s/Div)
Time (100s/Div)
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RT8012A
Regulator 1 Ripple
VIN = 5V, VOUT = 3.3V, IOUT = 1A L = 3.3uH, COUT = 10uF
Preliminary
Regulator 2 Ripple
VIN = 5V, VOUT = 1.2V, IOUT = 1.5A L = 2.2uH, COUT = 10uF
VOUT (10mV/Div)
VOUT (10mV/Div)
VLX (5V/Div)
VLX (5V/Div)
Time (1s/Div)
Time (1s/Div)
Regulator 1 Power On from EN
Regulator 2 Power On from EN
VEN (2V/Div) VOUT (2V/Div) I IN (500mA/Div)
VEN (2V/Div) VOUT (2V/Div) I IN (500mA/Div)
VIN = 5V, VOUT = 3.3V, IOUT = 1A
VIN = 5V, VOUT = 1.2V, IOUT = 1.5A
Time (1ms/Div)
Time (1ms/Div)
Regulator 1 Power On from VIN
Regulator 2 Power On from VIN
VIN (2V/Div) VOUT (2V/Div)
VIN (2V/Div) VOUT (2V/Div)
IOUT (500mA/Div)
VIN = 5V, VOUT = 3.3V, IOUT = 1A
IOUT (500mA/Div)
VIN = 5V, VOUT = 1.2V, IOUT = 1.5A
Time (1ms/Div)
Time (1ms/Div)
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Preliminary
RT8012A
Regulator 2 Power Good Delay
Regulator 1 Power Good Delay
VIN (2V/Div) VOUT (2V/Div) PGOOD (5V/Div) IOUT (1A/Div)
VIN (2V/Div) VOUT (2V/Div) PGOOD (5V/Div) IOUT (1A/Div)
VIN = 5V, VOUT = 3.3V, IOUT = 1A
VIN = 5V, VOUT = 1.2V, IOUT = 1.5A
Time (1ms/Div)
Time (1ms/Div)
Regulator 1 Load Regulation
3.340 3.339 3.338
Regulator 2 Load Regulation
1.230 1.228 1.226
Output Voltage (V)
3.337 3.336 3.335 3.334 3.333 3.332 3.331 3.330 0.0 0.1 0.2 0.3 0.4 0.5
Output Voltage (V)
VIN = 5V, VOUT = 3.3V
0.6 0.7 0.8 0.9 1.0
1.224 1.222 1.220 1.218 1.216 1.214 1.212 1.210 0.00 0.25 0.50 0.75 1.00 1.25 1.50
VIN = 5V, VOUT = 1.2V
Output Current (A)
Output Current (A)
Regulator 1 Output Voltage vs. Temperature
3.36 3.35
Regulator 2 Output Voltage vs. Temperature
1.24 1.23
Output Voltage (V)
Output Voltage (V)
VIN = 5V, VOUT = 3.3V, IOUT = 0A
-50 -25 0 25 50 75 100 125
3.34 3.33 3.32 3.31 3.3 3.29 3.28
1.22 1.21 1.20 1.19 1.18 -50 -25 0
VIN = 5V, VOUT = 1.2V, IOUT = 0A
25 50 75 100 125
Temperature (C)
Temperature (C)
DS8012A-01 March 2007
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RT8012A
Preliminary
Switching Frequency vs. Input Voltage
1400 1350
Switching Frequency vs. Temperature
1400 1350
Frequency (kHz)
Frequency (kHz)
1300 1250 1200 1150 1100 1050 1000
1300 1250 1200 1150 1100 1050
VOUT = 1.2V, IOUT = 300mA
2.5 3 3.5 4 4.5 5 5.5
1000
VIN = 5V, VOUT = 1.2V, IOUT = 300mA
-50 -25 0 25 50 75 100 125
Input Voltage (V)
Temperature (C)
Regulator 1 Inductor Peak Current vs. Input Voltage
2.3 2.2
Regulator 2 Inductor Peak Current vs. Input Voltage
3.0 2.9
Inductor Peak Current (A)
2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 4
Inductor Peak Current (A)
2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0
VOUT = 3.3V
4.3 4.6 4.9 5.2 5.5
VOUT = 1.2V
2.5 3 3.5 4 4.5 5 5.5
Input Voltage (V)
Input Voltage (V)
Regulator 1 Current Limit vs. Temperature
1.8 1.7
Regulator 2 Current Limit vs. Temperature
2.5 2.4 2.3
Output Current (A)
Output Current (A)
1.6 1.5 1.4 1.3 1.2 1.1 1.0
2.2 2.1 2.0 1.9 1.8 1.7
VIN = 5V, VOUT = 3.3V
-50 -25 0 25 50 75 100 125
1.6 1.5
VIN = 5V, VOUT = 1.2V
-50 -25 0 25 50 75 100 125
Temperature (C)
Temperature (C)
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DS8012A-01 March 2007
Preliminary Applications Information
The basic RT8012A application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current IL increases with higher VIN and decreases with higher inductance.
RT8012A
current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy. However, they are usually more expensive than the similar powered iron inductors. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : IRMS = IOUT(MAX) VOUT VIN VIN -1 VOUT
V V IL = OUT x 1 - OUT VIN f xL
Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is IL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation :
VOUT VOUT L= x 1 - VIN(MAX) f x IL(MAX)
Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard", which means that inductance collapses abruptly when the peak design
This formula has a maximum at VIN = 2VOUT, where I RMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, VOUT, is determined by :
1 VOUT IL ESR + 8fCOUT
DS8012A-01 March 2007
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RT8012A
Preliminary
For adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : VOUT = VREF (1 + R1) R2 where VREF is the internal reference voltage (0.8V typ.) Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as : Efficiency = 100% - (L1+ L2+ L3+ ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VIN quiescent current appears due to two factors including the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge Q moves from VIN to ground. The resulting Q/t is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, R SW and external inductor R L.In continuous mode, the average output current flowing
DS8012A-01 March 2007
The output ripple is highest at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Selecting Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Output Voltage Programming The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 3.
V OUT R1 FB RT8012A GND R2
Figure 3. Setting the Output Voltage
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Preliminary
through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows : RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1-DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Thermal Considerations For continuous operation, do not exceed the maximum operation junction temperature 125C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature differential between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) - TA ) / JA Where T J(MAX) is the maximum operation junction temperature 125C, TA is the ambient temperature and the JA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8012A, where T J(MAX) is the maximum junction temperature of the die (125C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance JA is layout dependent. For WQFN-16L 4x4
DS8012A-01 March 2007
RT8012A
packages, the thermal resistance JA is 54C/W on the standard JEDEC 51-7 four-layers thermal test board. The maximum power dissipation at TA = 25C can be calculated by following formula : PD(MAX) = ( 125C - 25C) / 54C/W = 1.852W for WQFN-16L 4x4 packages The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance JA. For RT8012A packages, the Figure 4 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed.
2.0
Maximum Power Dissipation (W)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75
Four Layers PCB WQFN 16L 4x4
100
125
Temperature (C)
Figure 4. Derating Curves for RT8012A Packages Layout Considerations Follow the PCB layout guidelines for optimal performance of RT8012A. Keep the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins (VIN and GND). LX node is with high frequency voltage swing and should be kept small area. Keep analog components away from LX node to prevent stray capacitive noise pick-up. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT8012A. Connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors.
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RT8012A
Outline Dimension
Preliminary
D
D2
SEE DETAIL A L
1
E
E2
1
1 2
e A A1 A3
b
2
DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.
Symbol A A1 A3 b D D2 E E2 e L
Dimensions In Millimeters Min 0.700 0.000 0.175 0.250 3.950 2.000 3.950 2.000 0.650 0.500 0.600 Max 0.800 0.050 0.250 0.380 4.050 2.450 4.050 2.450
Dimensions In Inches Min 0.028 0.000 0.007 0.010 0.156 0.079 0.156 0.079 0.026 0.020 0.024 Max 0.031 0.002 0.010 0.015 0.159 0.096 0.159 0.096
W-Type 16L QFN 4x4 Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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DS8012A-01 March 2007

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